The present invention relates to a semiconductor memory device, and more specifically to a data output circuit differentiating global data lines according to an operation mode to output them to data input/output pins.
In general, in the case of a semiconductor memory device such as DDR SDRAM, it includes thirty-two data input/output pins (DQ) and thirty-two global input/output lines gin to support (X32, X16, and X8) data width options.
Herein, an operation mode X32 uses thirty-two data input/output pins (DQ), an operation mode X16 uses sixteen data input/output pins (DQ), and an operation mode X8 uses eight data input/output pins (DQ).
Accordingly, when data is read in the semiconductor memory device, an assignment of the corresponding data input/output pin (DQ) per a global input/output line (gio) can be changed according to an operation mode, that is, data width option. For example, in the operation mode X32, the data signals output from the respective global input/output lines (gio) are connected one to one to the data input/output pins (DQ) However, in the operation mode X16 or X18, any one of the data signals output to a plurality of global input/output lines gio is selected to be transferred to a specific data input/output pin (DQ). A circuit performing such a multiplexing process to select and transfer data to the data input/output pin (DQ) is a data output circuit.
FIG. 1 is a block view showing a data output circuit of a conventional semiconductor memory device, wherein it shows a structure that performs a multiplexing corresponding to four global input/output lines (gio<0:3>) to support the operation modes X32, X16, and X8. Therefore, eight data output circuits as in FIG. 1 are further included.
Referring to FIG. 1, the data output circuit 1 is includes a multiplexer circuit 10 and a multiplexer driver 20.
The multiplexer circuit 10 comprises an X32 multiplexer 12, an X16 multiplexer 14, and an X8 multiplexer 16, of which output terminals are commonly connected to a node A.
The X32 multiplexer 12 selects and outputs the data of a global input/output line (gio<0>) in response to the operation mode X32, the X16 multiplexer 14 selects and outputs any one of the data of a global input/output lines (gio<0:1>) in response to the operation mode X16, and the X8 multiplexer 16 selects and outputs any one of the data of global input/output lines (gio<0:3>) in response to an operation mode X8.
The multiplexer driver 20 transfers MUX output signals (MXOUT) amplifying data signals output from a node A to the data input/output pins (DQ).
FIGS. 2a to 2c are views showing each constitution of an X32 multiplexer 12, an X16 multiplexer 14, and an X8 multiplexer 16 constituting the multiplexer circuit 10 of FIG. 1.
First, referring to FIG. 2a, the X32 multiplexer 12 comprises a tri-state inverter (INV1) input with data signals of the global input/output line (gio<0>) and applies an operation mode X32 and an inverted operation mode X32 to the tri-state inverter to control the output of the tri-state inverter (INV1). Therefore, the X32 multiplexer 12 outputs the data signal of the global input/output line (gio<0>).
Next, referring to FIG. 2b, the X16 multiplexer 14 comprises tri-state inverters (INV2 and INV3). Each tri-state inverter is inputted with data signals of global input/output lines (gio<0:1>). A first address signal addA applied from the operation mode X16 controls the output of the tri-state inverters INV2 and INV3.
Therefore, the X16 multiplexer 14 outputs any one of the data signals of the global input/output lines (gio<0:1>). In other words, when the first address signal (addA) is in a high state, the data signal of the global input/output line (gio<0>) is output by turning on the tri-state inverter (INV2), and when the first address signal (addA) is in a low state, the data signal of the global input/output line (gio<1>) is output by turning on the tri-state inverter (INV3).
Referring to FIG. 2c, the X8 multiplexer 16 comprises tri-state inverters (INV4, INV5, INV6, and INV7), in which each input with data signals of global input/output lines (gio<0:3>). A first and second address signals addA and addB applied from an operation mode X8 controls the output of the tri-state inverters (INV4, INV5, INV6, and INV7).
Therefore, the X8 multiplexer 16 outputs any one of the data signals of the global input/output lines (gio<0:3>). In other words, when both the first and second address signals (addA and addB) are in a high state, the data signals of the global input/output line (gio<0>) are output by turning on the tri-state inverter (INV4), and when the first address signal (addA) is in a low state and the second address signal (addB) is in a high state, the data signal of the global input/output line (gio<1>) is output by turning on the tri-state inverter (INV5). And, when the first address signal (addA) is in a high state and the second address signal (addB) is in a low state, the data signal of the global input/output line (gio<2>) is output by turning on the tri-state inverter (INV6), and when both the first and second address signals (addA and addB) are in a low state, the data signal of the global input/output line (gio<3>) is output by turning on the tri-state inverter (INV7).
As described above, the conventional data output circuit comprises the plurality of multiplexers (X32, X16, and X8), and selectively operates any one multiplexer thereof according to the operation modes so that the selected multiplexer selects and outputs the signals of the corresponding global input/output lines and amplifies them in response to the multiplexer driver 20 to transfer them to the data input/output pin (DQ).
However, in the conventional data output circuit, some of the data signals of the global input/output lines (gio<0:3>), for example, the data signal of the global input/output line (gio<0>), is commonly connected to the plurality of multiplexers (X32 multiplexer 12, X16 multiplexer 14, and X8 multiplexer 16), the entire loading of the global input/output line (gio<0>) becomes large, thereby, causing a problem that the delay occurs.
Also, the signals of the output terminal node A are connected to a gate cap of the multiplexer driver 20 as well as the plurality of multiplexers (X32 multiplexer 12, X16 multiplexer 14, and X8 multiplexer 16) constituting the neighboring multiplexer circuit 10, causing a problem that delay increases due to the affect of the junction cap existing therebetween.
Therefore, such an increase of delay slows down the data read speed of the semiconductor memory device so that it serves as an obstacle in increasing the data read speed of the semiconductor memory device.